`ifndef SVC_MODULE_NAME_SV
`define SVC_MODULE_NAME_SV

`include "svc.sv"

module svc_module_name #(
    parameter WIDTH = 32
) (
    input  logic             clk,
    input  logic             rst_n,

    input  logic             in_valid,
    input  logic [WIDTH-1:0] in_data,
    output logic             in_ready,

    output logic             out_valid,
    output logic [WIDTH-1:0] out_data,
    input  logic             out_ready
);
  //
  // Localparams
  //

  //
  // Internal signals
  //
  logic [WIDTH-1:0] data_next;

  //
  // Child module instantiations
  //

  //
  // Combinational logic
  //
  always_comb begin
    data_next = in_data;
  end

  //
  // Sequential logic
  //
  always_ff @(posedge clk) begin
    if (!rst_n) begin
      out_valid <= 1'b0;
      out_data  <= '0;
    end else begin
      // Logic here
    end
  end

endmodule

`endif