ReddRadar
Agent skill
hls-cpp-to-rtl
Expert skill for C/C++ to RTL conversion using High-Level Synthesis tools
Install this agent skill to your Project
npx add-skill https://github.com/a5c-ai/babysitter/tree/main/library/specializations/fpga-programming/skills/hls-cpp-to-rtl
SKILL.md
HLS C/C++ to RTL Skill
Overview
Expert skill for High-Level Synthesis (HLS) development, converting C/C++ algorithms to optimized RTL implementations for FPGA acceleration.
Capabilities
- Write HLS-synthesizable C/C++ code
- Apply Vitis HLS pragmas (PIPELINE, UNROLL, ARRAY_PARTITION)
- Optimize loop initiation interval (II)
- Configure HLS interface synthesis (AXI-MM, AXI-Stream, AXI-Lite)
- Analyze HLS reports and iterate on design
- Apply dataflow optimization
- Handle fixed-point arithmetic (ap_fixed, ap_int)
- Integrate HLS IP into Vivado block designs
Target Processes
- hls-development.js
- hardware-software-codesign.js
- ip-core-integration.js
Usage Guidelines
Code Structure
- Use static arrays for memory inference
- Avoid dynamic memory allocation
- Structure loops for pipeline optimization
- Use ap_int/ap_uint for arbitrary precision
Key Pragmas
#pragma HLS PIPELINE II=1- Pipeline loops for throughput#pragma HLS UNROLL factor=N- Unroll loops for parallelism#pragma HLS ARRAY_PARTITION- Memory partitioning#pragma HLS DATAFLOW- Task-level parallelism#pragma HLS INTERFACE- Port protocol specification
Interface Synthesis
- AXI4-Lite: Control registers and scalar arguments
- AXI4 Memory-Mapped: Large data arrays
- AXI4-Stream: Streaming data interfaces
- ap_none/ap_vld/ap_hs: Simple handshake protocols
Optimization Flow
- Baseline functional implementation
- Analyze synthesis report
- Identify bottleneck (II, latency, resources)
- Apply targeted optimizations
- Iterate until QoR targets met
Dependencies
- Vitis HLS CLI awareness
- C/C++ language expertise
- FPGA resource understanding
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